1. Field of the Invention
Embodiments of the present disclosure relate to display technology, and more particularly to an array substrate and a liquid display device with the same.
2. Discussion of the Related Art
Film-type patterned retarder (FPR) is an imaging method of current 3D liquid crystal display. As shown in FIG. 1, the FPR display system includes a down substrate 11, an up substrate 12, and a patterned retarder film 13. The down substrate 11 and the up substrate 12 form a liquid crystal panel including an imaging unit 14 for displaying images. The imaging unit 14 includes a left image unit 141 corresponding to a pixel for displaying a left eye image and a right image unit 142 corresponding to a pixel for displaying a right eye image. The patterned retarder film 13 is adhesively attached to the liquid, crystal panel. The patterned retarder film 13 cooperates with a polarized glass 16 to split the 3D image to the left eye image 21 and the right eye image 22, and then transmits the images to viewers. However, under a 3D display mode crosstalk may exist when the viewer is at a wide viewing angle. For example, the left eye image 21 is also observed by the right eye. Usually, the solution is to increase the width of the black matrix 15 between the left image unit 141 and the right image unit 142. In addition, the width of the black matrix 15 has to be increased to some degree so that the crosstalk may be reduced.
For a multi-domain vertical alignment (MVA) display, a larger color shift exists when the viewing angle is large. Generally, a charge-shared technology is adopted to obtain a low color shift. As shown in FIG. 2, a pixel (N) is divided into a main pixel (N) and a secondary pixel (N). One pixel (N) 30 corresponds to two scanning lines (N), (M) turn on at different time. Thin-film transistors 31, 32 are turn on when the scanning lines are at high level. A data line (x) transmits voltage signals to the main pixel (N) and the secondary pixel (N) via the thin-film transistors 31, 32 at the same time such that the level of the main pixel (N) and the secondary pixel (N) are the same. After the scanning line (N) is closed, the high level is input to the scanning line (M) to turn on the thin-film transistors 33. An input of the thin-film transistor 33 connects to the pixel electrode of the secondary pixel (N). An output of the thin-film transistors 33 connects to one end of the storage capacitor 34. The other end of the storage capacitor 34 connects to the common electrode on another substrate. When the liquid crystal panel is driven, the polarity switches between a positive voltage and a negative voltage. Before the thin-film transistors 33 is turn on, the polarity of the charges is opposite to that of the charges of the current secondary pixel (N). Thus, after the thin-film transistors 33 is turn on, the charges of the secondary pixel (N) are neutralized by the storage capacitor 34 to decrease the electrical field of the secondary pixel (N). As such, there is a difference between the electrical fields of the main pixel (N) and the secondary pixel (N) and the color shift is reduced at wide viewing angle.
However, by adopting the above charge-shared technology, the two scanning lines (N), (M) of the pixel (N) 30 are arranged between the main pixel (N) and the secondary pixel (N). The Thin-film transistors 31, 32 connected with the scanning line (N) and the transistors 33 and the storage capacitor 34 connected with the scanning line (M) are arranged between the main pixel (N) and the secondary pixel (N). As shown in FIG. 3, the main dark area 35 corresponding to an opaque area is arranged between the main pixel (N) and the secondary pixel (N) of the pixel (N) 30. The width of the main dark area 35 is larger than that of the dark area 36 between the pixel (N) 30 and the pixel (N+1) 40. When the FRP 3D display technology is applied to the MVA panel, the width of the corresponding black matrix 15 between the left image unit 141 and the right image unit 142 is smaller, which does not helpful to reduce the crosstalk. Thus, the charge-shared technology is not suitable for the FPR 3D display mode.
In another design as shown in FIG. 4, one pixel (N) 50 includes the main pixel (N) and the secondary pixel (N). Two corresponding scanning lines are arranged in the same side of the pixel (N) 50. Wherein the scanning line (N) connects to the pixel electrodes of the main pixel (N) and the secondary pixel (N) via the thin film transistors 51, 52. The scanning line (M) connects to the pixel electrode of the secondary pixel (N) via the thin film transistor 51, 53. The output of the thin film transistor 53 connects to the storage capacitor 54. The corresponding scanning lines and thin film transistors of the pixel (N) 50 are arranged on the same side of the pixel (N) 50. As shown in FIG. 5, the distance between the pixel (N) 50 and the pixel (N1) 60 is large. That is, the width of the main dark area 57 is large. When the FPR 3D display technology is applied to the MVA panel, width of the black matrix 15 between the left image unit 141 and the right image unit 142 is large so that the crosstalk is reduced. As such, this charge-shared technology is more suitable for the FRP 3D display mode than that shown in FIG. 2.
However, with respect to the charge-shared technology shown in FIG. 4, a connection 55 connecting, to the pixel electrode of the secondary pixel (N) has to pass through the area where the main pixel (N) is located. In this way, a larger parasitic capacitance 56 is larger between the pixel electrodes of the main pixel (N) and the secondary pixel (N). The parasitic capacitance 56 may reduce the level of the main pixel (N) and the secondary pixel (N). In addition, in the process of 4PEP, the parasitic capacitance 56 changes due to the being radiated by lights. As such, the reliability of the liquid crystal display is reduced. In addition, as the connection 55 passes through the area where the main pixel (N) is located, the transmission rate and the aperture rate are reduced.